Photonic Device
Fabrication
Waveguides, gratings, resonators and couplers fabricated from your GDS on silicon nitride or silicon-on-insulator platforms: e-beam or stepper lithography, ICP-RIE with measured sidewalls, PECVD or ALD cladding, thermo-optic heaters, edge-coupler facets and V-grooves for fiber attach. From one wafer to pilot lots, with the metrology defined before the run.
platforms
with e-beam
diameters
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The passive and thermo-optic building blocks of a photonic chip
Each device on this page is a defined sequence of deposition, lithography, etch and cladding, with sidewall roughness and dimensional control as the quality measures. We run that sequence to your layout and report what was measured.
Schematic, not to scale: a strip waveguide core in SiN or Si on buried oxide, top cladding by PECVD or ALD oxide, optional metal heater above the cladding. Core dimensions and cladding thickness are set by your design.
Silicon nitride waveguides
LPCVD or PECVD SiN cores on thermal oxide, patterned by e-beam or stepper and etched by ICP-RIE; low-stress nitride for thick cores, index reported per lot.
SOI waveguides and gratings
Strip and rib waveguides, grating couplers and Bragg structures in the SOI device layer with full or partial etch depths; sidewall angle and roughness measured.
Ring resonators and couplers
Rings, directional couplers and MMIs with gap control by e-beam lithography; CD and gap reported against the layout.
Cladding
PECVD SiO₂ top cladding, or ALD SiO₂ where narrow gaps must be filled conformally; gap-fill feasibility reviewed for the geometry. See ALD and PECVD.
Heaters and metal
Thermo-optic heaters (TiN, NiCr, Pt) and contact metal above the cladding, with pads for probing or wire bonding.
Facets, V-grooves and dicing
Edge-coupler facets by etch or polish, V-grooves for fiber attach, stealth dicing for chip separation. See optical benches.
Photonic Device Fabrication
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical ranges
Values are typical process windows; the quotation states the specification and the measurements for your layout.
| Parameter | Typical | Note |
|---|---|---|
| Platforms | SiN on oxide (200-800 nm cores), SOI (220 nm and other device layers), silica-on-silicon | Customer wafers or sourced |
| Lithography | E-beam for sub-100 nm features and gaps; stepper or contact for larger | Field stitching reviewed for long devices |
| Etch | ICP-RIE with full and partial depths; sidewall angle and roughness measured | See ICP-RIE |
| Cladding | PECVD SiO₂ 1-3 µm; ALD SiO₂ for gap fill | Stress balanced per stack |
| Heaters | TiN, NiCr or Pt with Al or Au pads | Resistance reported |
| Wafer size | 4 to 8 inch; pieces for feasibility | Chip-level delivery by stealth dicing |
| Metrology | SEM, AFM roughness, ellipsometry, optical microscopy; optical test by agreement | Defined before the run |
From GDS to measured chips
- 01ReviewLayout, platform, critical dimensions and gaps, cladding and heater needs.
- 02DefineProcess sequence with the metrology plan; coupon run for new combinations.
- 03FabricateDeposition, lithography, etch, cladding, metal in the agreed order.
- 04MeasureCD, sidewall, roughness, film thickness and index as agreed.
- 05Dice and deliverChips by stealth dicing with facets prepared where required.
Questions engineers ask before ordering
Do you also test the optical performance?
Fabrication metrology (CD, sidewall, roughness, film data) is standard. Optical testing such as propagation loss or coupler efficiency is quoted separately as an agreed item.
Can you run my SOI wafers?
Yes, customer SOI and SiN wafers are accepted after a review of the device layer, oxide and surface condition; we can also source them.
What do you need to quote?
GDS with layer map, platform and layer thicknesses, minimum feature and gap, cladding and heater needs, facet or V-groove requirement, quantity and date.
Processes usually combined with this work
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.