Backside Metallization (BSM)
Ti/Ni/Ag, Ti/Ni/Au and Ti/Cu Stacks
Sputtered backside metal for die attach, thermal path and backside contact on thinned and bumped wafers: an adhesion layer, a barrier and a solderable finish chosen for your die-attach method, with front-side protection, stress relief and inspection in the same program. For power discretes, SiC and GaN, LED and laser die, and RF die with a backside ground.
die-attach method
minimum on carrier
diameters
finishes
Choose the stack by the die-attach method
The finish must match the solder or sinter material that lands on it, the barrier keeps that solder from consuming the stack, and the adhesion layer ties everything to the silicon. We confirm the stack and thicknesses against your die-attach process before deposition. For SiC and other compound semiconductors, ohmic-contact formation and solderable backside overmetallization are reviewed separately: the contact material, anneal and electrical acceptance criteria are agreed for each device.
Swipe horizontally to view the full diagram.
Schematic; layer thicknesses are set per specification.
Ti/Ni/Ag and Ti/Ni(V)/Ag
Soft-solder die attach, the most common power-discrete stack. The Ag finish protects solderability for SnAg, SAC and selected high-Pb solders; the Ni or Ni(V) layer is a solderable diffusion barrier whose thickness is selected to accommodate reaction with the solder during reflow and service. Ni(V) is used where a non-magnetic sputter target is preferred.
Ti/Ni/Au
AuSn eutectic and Au-rich attach. The Au thickness is selected for the solder volume, alloy composition and thermal profile; for AuSn attachment, dissolved Au from both mating surfaces is included in the joint-composition review. Used with AuSn preforms, AuSn-bumped die and for Au wire or ribbon on the backside. See AuSn bumps.
Ti/Pt/Au
Adhesion, barrier and Au finish for selected die-attach applications and higher service temperatures. For electrical backside contacts, the contact scheme and any anneal are qualified for the semiconductor, conductivity type, doping and required contact resistance. See ohmic contacts.
Ti/Cu and thick Cu
Cu sinter and plated backsides. Sputtered Ti/Cu as the seed for electroplated Cu or for Ag and Cu sintered attach; Cu thickness by plating. See electroplating.
Alloy finishes: AuSn, AuGe, AuSi
Solder carried by the die. Blanket AuSn, AuGe or AuSi on the backside when the attach solder is to come with the die rather than as a preform. See AuGe and AuSi die attach.
Bumped and thinned wafers
Front-side protection by tape or a temporary carrier, backgrinding to the target thickness, stress relief, then BSM; bump height and reflow temperature are reviewed per program. See wafer thinning.
Backside Metallization
Scope and specification options. Every figure is confirmed for your program in the quotation.
From incoming wafer to metallized backside
Seven steps, run in order. Oxide removal is either an in-vacuum Ar sputter clean immediately before the Ti, or an HF-based wet clean followed by deposition within a qualified interval.
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Schematic; the route (tape or carrier) and the stack are fixed at the incoming review.
| Step | What happens | What is checked |
|---|---|---|
| 1. Incoming review | Front-side structures, bump height, incoming thickness, bow, requested stack | Stack and route confirmed in writing |
| 2. Front-side protection | UV tape or film for standard-thickness wafers; temporary carrier for thin wafers or tall bumps | Protection matched to bump height and process temperature |
| 3. Backgrind and stress relief | Grinding to the target thickness, then dry polish, CMP or wet etch to remove grinding damage | Thickness, TTV, bow |
| 4. Oxide removal | In-vacuum Ar sputter clean immediately before the Ti, or HF-based wet clean with a qualified interval to deposition | Surface condition, time to deposition |
| 5. Sputter stack | Ti, then Ni or Ni(V), then Ag or Au in one vacuum sequence; Cu where the stack calls for it | Thickness by XRF or step height, sheet resistance |
| 6. Inspection | Adhesion by tape test to the agreed method, visual inspection, thickness map; die shear or contact resistance on test die on request | Report with the lot |
| 7. Debond, tape, dicing | Debond and clean, mount on tape or frame, dicing or delivery as whole wafers | Final thickness, die edge condition |
Typical ranges
Thicknesses and process temperature depend on the die-attach process and on what is on the front side; the quotation states the values for your wafers.
| Parameter | Typical | Note |
|---|---|---|
| Adhesion layer | Ti 50 to 150 nm | Cr on request |
| Barrier | Ni or Ni(V) 200 to 500 nm; Pt 50 to 200 nm | Thicker Ni by plating |
| Finish | Ag 300 nm to 1 µm; Au 50 to 200 nm; Cu 0.5 to 2 µm sputtered, thicker by plating | Set by the solder or sinter material |
| Deposition | DC magnetron sputtering in one vacuum sequence; e-beam evaporation for Au-based stacks | Oxide removal immediately before |
| Process temperature | Kept below the front-side limit (bump solidus, polymer cure) | Confirmed per program |
| Wafer size | 4 to 12 inch | Pieces for feasibility |
| Wafer thickness | As received; 150 to 300 µm free-standing; 50 to 100 µm on carrier | Thinner on inquiry |
| Front side | Pads, polyimide, or bumps (SnAg, AuSn, Cu pillar, Au) | Protection method per bump height |
| Materials | Si, SOI, SiC, GaN-on-Si, GaAs, InP | Available diameter and thickness combinations confirmed per material |
| Inspection | Thickness (XRF or step height), sheet resistance, tape test, visual | Die shear or contact resistance on request |
| Delivery | Whole wafers on tape or frame, diced die, or thinned wafers on carrier | Dicing in the same program |
BSM after bumping, with the front side protected
Backside metal is often the last wafer-level step, after the bumps are on the front. Two routes: standard-thickness wafers with moderate bump heights go on UV tape or a protective film and are ground and metallized in that state; thin wafers and tall bumps are mounted on a temporary carrier, so the bumps sit in the adhesive while the backside is ground and metallized, then debonded. Reflowed bumps set the ceiling for every later step, so sputtering runs below the bump solidus and the carrier adhesive is chosen to that limit.
Swipe horizontally to view the full diagram.
Schematic; the route is chosen at the incoming review from wafer thickness, bump height and process temperature.
Where backside metal is specified
Power discretes
Vertical MOSFET, IGBT, Schottky diode and fast-recovery diode die, where the backside forms the drain, collector or cathode and provides the thermal path. Ti/Ni/Ag as the standard stack.
SiC and GaN power
Thinned SiC and GaN-on-Si wafers with Ti/Ni/Ag or Ti/Ni/Au as the solderable overmetallization; where an ohmic contact is required, its contact material, anneal and electrical acceptance are reviewed separately. See SiC wafer processing and GaN and III-V.
LED and laser die
Ti/Pt/Au or Ti/Ni/Au for eutectic attach on submounts. See laser submounts.
RF and photonics die
Backside ground planes and TSV backside metal on GaAs, GaN and silicon photonics. See TSV reveal.
Thinned logic and memory
Ag or Au finish on thinned die for solder attach in stacked packages.
Test chips and thermal test vehicles
Backside-metallized test die for die-attach and thermal evaluation. See thermal test chips.
For a BSM quotation
| Item | What helps |
|---|---|
| Wafer | Material, diameter, incoming thickness, bow, quantity |
| Front side | Pads or bumps, bump material and height, polymer layers, reflow history |
| Stack | Requested layers and thicknesses, or the die-attach process so that we can propose a stack |
| Electrical contact | Conductivity type, doping and existing backside layers; required contact resistance when the backside is an electrical contact |
| Die attach | Attach alloy or paste, and the attachment temperature, time, pressure and atmosphere |
| Acceptance | Thickness uniformity, edge exclusion, post-deposition bow or warp, surface roughness, adhesion and electrical acceptance criteria |
| Target | Final thickness and delivery format |
| Constraints | Maximum process temperature, chemicals to avoid |
| Handling | Storage, packaging and allowable time before attachment, especially for tarnish-sensitive finishes |
| Quantity | Wafers and target date |
Processes usually combined with this work
Questions engineers ask before ordering
Ag or Au finish?
Ag finishes are commonly used with Sn-based solders such as SnAg and SAC, and with selected high-Pb solders; Au for AuSn eutectic and Au-rich attach. We confirm the finish and its thickness against your die-attach process, since a thick Au finish can embrittle a Sn-based joint.
Can you metallize wafers that already have bumps?
Yes. The front side is protected by tape or a temporary carrier, sputtering stays below the bump solidus, and bump height and reflow history are reviewed per program.
How thin can the wafer be?
Standard-thickness wafers as received, 150 to 300 µm free-standing, 50 to 100 µm on a temporary carrier; thinner on inquiry.
How is the metal checked?
Thickness by XRF or step height, sheet resistance, adhesion by tape test to the agreed method, and visual inspection; die shear or contact resistance on test die on request. A report accompanies the lot.
What temperature does the wafer see?
Sputtering is run at low temperature and kept below the limit set by the front side, such as the bump solidus or a polymer cure; the quotation states the value for your wafers.
Start your BSM project.
Initial response typically within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.