Superconducting Thin-Film and
Flip-Chip Process Modules
Niobium and tantalum films deposited and patterned on high-resistivity silicon and sapphire, dielectric stacks, through-silicon vias, wafer bonding, and indium or AuSn bump interfaces, so a resonator or qubit chip can be stacked or packaged for cryogenic test. Process development and small lots for groups that need a repeatable film, etch and packaging flow. We do not run a public quantum PDK or a millikelvin test service.
deposited per program
supplied or sourced
interfaces
minimum order
What we run, and what we do not
Superconducting device work is a set of process modules that each need control: film purity and stress, etch profile and residue, dielectric loss, and the interconnect that survives cool-down. We quote the modules your group needs and state the limits plainly.
Schematic, not to scale: a Nb or Ta device chip on HR-Si or sapphire, bumped with indium or AuSn onto a carrier that carries TSV and wiring; airbridges optional. Bump pitch, TSV size and cryogenic test are set per program.
Nb and Ta thin films
Sputtered niobium and tantalum on high-resistivity silicon and sapphire with dedicated targets procured for the program; thickness, stress and resistivity reported per lot. Other superconducting films reviewed.
Patterning and etch
Contact, stepper or e-beam lithography as the layer needs, ICP-RIE for resonators, feedlines, ground planes and wiring, with residue-sensitive cleans. See ICP-RIE.
Dielectrics
ALD Al₂O₃ and PECVD or LPCVD SiO₂ and SiN where a crossover, capacitor or passivation is required; dielectric choice reviewed against loss.
TSV and bonding
Through-silicon vias for carrier and readout wafers, and wafer bonding for stacked modules. See TSV and bonding.
Indium and AuSn flip-chip
Indium bumps for cryogenic flip-chip and AuSn for fluxless assembly, with thermocompression bonding of device to carrier. See indium bumping and flip-chip.
Not offered
Millikelvin or cryogenic electrical test, a public superconducting PDK or MPW, and Josephson junction critical-current control as a standard specification; junction work is a custom development discussion with your metrology.
Superconducting Thin-Film and Flip-Chip Process Modules
Scope and specification options. Every figure is confirmed for your program in the quotation.
Typical ranges
Film and device figures are confirmed on your substrate; the quotation states the specification and the room-temperature measurements delivered.
| Parameter | Typical | Note |
|---|---|---|
| Films | Nb, Ta; NbN, NbTiN and Al reviewed per program | Targets procured per program; stress and resistivity reported |
| Thickness | 50-300 nm typical; thicker by agreement | Uniformity per lot |
| Substrates | High-resistivity silicon (float-zone or HR CZ), sapphire, fused silica; 2 inch to 300 mm and pieces | Cleaning sequence per surface |
| Lithography | Contact for wiring and pads; stepper and e-beam for fine resonator and coupler features | Feature size per tool set |
| Etch | ICP-RIE with fluorine or chlorine chemistries; profile and residue checked by cross section | Sidewall angle measured |
| Interconnect | TSV, indium bumps, AuSn bumps, airbridges by lift-off | Pitch per layout |
| Room-temperature metrology | Thickness, sheet resistance, film stress, optical and SEM inspection | Cryogenic results are yours to measure |
From film specification to packaged chips
- 01DefineFilms, substrate, layers, interconnect, what you will measure cold.
- 02Qualify the filmTarget procurement, deposition trials, stress and resistivity on coupons.
- 03PatternLithography and ICP-RIE of resonators, wiring and bumps; dielectrics where needed.
- 04InterconnectTSV, bonding, indium or AuSn flip-chip to the carrier.
- 05DeliverChips or wafers with room-temperature data for your cryogenic test.
Questions engineers ask before ordering
Can you fabricate Josephson junctions?
Not as a standard specification. Junction critical-current control depends on tunnel-barrier and overlay control that we treat as a custom development with your metrology; resonators, wiring, dielectrics, TSV and flip-chip are the standard modules.
Do you test at cryogenic temperature?
No. We deliver room-temperature film and dimensional data; cryogenic performance is measured by you.
What do you need to quote?
Film and thickness, substrate and size, layer stack with feature sizes, interconnect needs (TSV, bumps, bonding), quantity and date, and which cold results you need the process to support.
Processes usually combined with this work
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.