Silicon Capacitor Prototyping:
Deep-Trench and 3D MIM
Capacitors built into the silicon itself: deep trenches, a conformal dielectric and electrode stack, contacts, thinning and terminations. We offer this as a process development program assembled from modules we run every day. Trench geometry, dielectric and layer count are set with you at design review, and the capacitance, leakage and breakdown the design achieves are established on the first development lot rather than promised in advance.
development lot
all in one program
MOS, MIM, multi-layer
leakage are established
Capacitance that is thin, close to the die, and stable over bias and temperature
Ceramic chip capacitors keep the bulk-capacitance job. A capacitor formed in silicon is chosen where the value must not collapse under DC bias, where the part must be thin enough to embed or stack, or where inductance has to be as low as placing the capacitor next to the die allows.
Schematic cross section of a deep-trench capacitor: doped substrate as bottom electrode, dielectric on the trench walls, top electrode filling the trench, terminals front and back. Not to scale; dimensions are set per design.
What a silicon capacitor gives
Capacitance that stays essentially flat under DC bias and drifts little with temperature, no piezoelectric noise, a thin die, and terminals that can sit micrometres from the load. The trade is cost per microfarad, which favours ceramics for bulk capacitance.
What we offer
A process development program, not a catalog part. We combine deep etching, dielectric and electrode deposition, metallization, thinning and dicing into one flow to your target value, footprint, voltage and termination, and we report what the first lot measures.
What we do not claim
A guaranteed capacitance density, voltage rating or reliability figure before a lot has been run. Those are outcomes of your geometry, dielectric and layer count, and they are confirmed by measurement on the development lot.
Where it starts
A target value, footprint, operating voltage and assembly method are enough for a feasibility answer within one business day; a GDS is not required for first contact.
Silicon Capacitor Prototyping: Deep-Trench and 3D MIM
Scope and specification options. Every figure is confirmed for your program in the quotation.
Three ways to build it
Voltage, target density and thermal budget decide between them at design review; a development wafer can carry more than one variant.
Trench MOS capacitor
Heavily doped silicon as the bottom plate, thermal SiO₂ or an oxide-nitride-oxide stack as the dielectric, doped polysilicon filling the trench. A high-temperature stack with the cleanest dielectric interface; the usual choice for voltage headroom and long-term stability.
Trench MIM capacitor
Atomic layer deposition builds the whole stack on the trench walls: TiN, a high-k film (Al₂O₃, HfO₂, ZrO₂ or laminates), and TiN again. Lower thermal budget and the highest density per layer; the usual choice for low-voltage decoupling next to a die.
Multi-layer MIM stack
The dielectric and electrode pair is repeated inside the same trench and alternate electrodes are tied together at the array edge, so each added layer acts in parallel with the first. Chosen when capacitance per footprint matters most; layer count is a development topic.
Wide-trench MIS with copper electrode
Wider trenches with an ALD dielectric, then barrier, seed and copper plating. A modest area gain, low series resistance from the thick copper, and the quickest route to an evaluation sample.
Design levers
Capacitance per footprint scales with the number of layers, the wall area the trenches add, and the dielectric constant over its thickness. Trench depth and pitch set the area gain, the dielectric sets density against voltage, stacking multiplies the result.
How the value is set
At design review we estimate the value from geometry and film constants and state the estimate as an estimate. The first development lot measures it, and later lots are adjusted against that measurement.
How the capacitance is engineered
Schematic: planar area, the extra wall area added by deep trenches, and a two-layer stack acting as capacitors in parallel. Multipliers depend on trench depth, pitch and layer count and are estimated per design.
From bare wafer to tested capacitor dies
Six modules in order, each of which has its own page on this site. The etch sets the area, the films inside the trench set the value and the voltage class, and the back end sets how the part is assembled. The same flow delivers etch-only trench test wafers when only the array is needed.
Schematic, not to scale. Pattern and deep etch, clean and smooth, dielectric, electrode, contacts and pads, then thinning, terminations, test and dicing. Dimensions, films and layer count are set per design.
- 01Pattern and deep etchHard mask, lithography, Bosch DRIE to the target depth. See deep silicon etching.
- 02Clean and smoothResidue removal and sidewall smoothing so the dielectric sees a clean, even surface.
- 03DielectricThermal SiO₂, ONO, or ALD high-k, conformal to the bottom of every trench. See ALD coating.
- 04ElectrodeDoped polysilicon, ALD TiN, or copper on barrier and seed; steps 3 and 4 repeat for a multi-layer stack.
- 05Contacts and padsElectrode patterning, contact metal, passivation with pad openings. See wafer metallization.
- 06Back endThinning on carrier where required, backside metal or bumps, wafer-level electrical test, dicing. See wafer thinning and UBM.
Delivered the way your assembly needs it
Terminations and die thickness are chosen for the assembly step that follows.
Schematic: bare die with wire-bond pads and backside metal, flip-chip die with bumps, thin die for embedding, and capacitor cells placed inside a silicon interposer next to TSVs and RDL.
Bare dies
Wire-bondable pads on the front and metallized back, for hybrid modules, submounts and evaluation.
Flip-chip dies
UBM with AuSn, Cu pillar and SnAg, or Au bumps, both terminals on the front, for photonic and RF modules, interposers and package substrates. See UBM.
Thin dies for embedding
Thinned on carrier with terminals matched to your substrate build-up, for capacitors embedded next to a processor. See wafer thinning.
Cells inside a silicon interposer
Decoupling cells placed in unused interposer area, next to TSVs and RDL, on the same wafer as the interposer. See interposers.
What the first lot reports
A capacitor program is judged by the measured value, not the drawing. The test plan is agreed at design review and its results are part of the delivery.
| Measurement | Scope | Note |
|---|---|---|
| Capacitance versus bias (C-V) | Wafer level, with wafer maps | Standard on the development lot |
| Leakage current and breakdown voltage | Wafer level, sampled per agreement | Standard on the development lot |
| Capacitance versus temperature | By agreement | Range and points defined in the quotation |
| Cross-section SEM | Trench depth, dielectric and electrode coverage | Standard on the development lot |
| Reliability (TDDB, HAST) | By agreement | Separate test program |
| RF characterization of bumped dies | By agreement | Fixture and method defined per program |
What is decided at design review
No figure below is a specification. Each is a choice made with you before the lot, then confirmed by what the lot measures.
| Parameter | Options and how it is set |
|---|---|
| Substrate | Heavily doped silicon, supplied with the program or customer-provided; resistivity chosen for the bottom electrode |
| Wafer size | 100 to 200 mm as standard; other formats reviewed |
| Trench geometry | Holes, slots or segmented slots; width, pitch, depth and array orientation set per design and confirmed by cross section |
| Aspect ratio | Set by the electrode fill route chosen; see the deep silicon etching page for the etch itself |
| Dielectric | Thermal SiO₂; ONO; ALD Al₂O₃, HfO₂, ZrO₂ and laminates; thickness chosen for the voltage class |
| Electrodes | In-situ doped polysilicon; ALD TiN; copper on barrier and seed for wide-trench builds |
| Layers | One MIM layer as the starting point; additional layers as a development step |
| Contact metal and terminations | Al, Ti/Au or Cu pads; backside metal; UBM with AuSn, Cu pillar and SnAg, or Au bumps |
| Final thickness | Per the assembly method; thinning on carrier where required |
| Delivery | Wafers at an agreed process stage, diced dies, or coupons, with wafer maps and cross-section reports |
| Lot size | From one wafer; pilot lots on the same flow after the process is frozen |
Where 3D silicon capacitors are used
AI and HPC power delivery
Decoupling cells in silicon interposers, bridge dies and package substrates, close to accelerator and switch dies. See AI and HPC packaging.
Integrated voltage regulators
Low-inductance capacitors for switching regulators and power stages that sit under or next to the processor, where ceramic parts no longer fit.
Silicon photonics and RF modules
Bias networks, DC blocks and broadband decoupling inside transceiver and laser modules, with AuSn-ready or Au terminations. See silicon photonics.
High-temperature, automotive and medical
Capacitance that holds its value over bias and temperature with no piezoelectric noise, for sensor front ends and prototypes in harsh environments.
Chiplets and custom ASICs
Package-level capacitance matched to the die layout rather than to a catalog footprint.
Research and process evaluation
3D capacitor and micro energy-storage research, ALD and etch development on real high-aspect-ratio structures, reference trench wafers for metrology. See test wafers.
What to send for feasibility review
| Item | What helps |
|---|---|
| Target | Capacitance per die and tolerance you need; whether a range is acceptable for the first lot |
| Geometry | Footprint and maximum die thickness |
| Voltage | Operating voltage and maximum voltage |
| Frequency | Frequency band, or inductance and resistance targets if known |
| Assembly | Wire bond, flip-chip or embedding, and the mating part |
| Quantity and date | Development lot size, pilot expectations, target schedule; GDS or sketch if available |
Questions engineers ask before ordering
Can you guarantee a capacitance value?
Not before a lot has been run. At design review we estimate the value from geometry and film constants and say so; the first development lot measures it, and later lots are adjusted against that measurement.
Do we need to supply a layout?
No. A target value, footprint, voltage and termination are enough to design the cell array with you; a customer GDS can also be run after a manufacturability review.
How does this differ from a TSV program?
The deep etch is shared. Instead of a copper via, the trench is lined with a capacitor stack and stays blind, so the wafer keeps its full thickness until the back end.
Have you delivered silicon capacitors before?
We offer them as a process development program built from modules we run in other programs: deep etching, thermal oxide and ALD dielectrics, polysilicon and TiN electrodes, metallization, thinning and dicing. The first lot for your design is where its figures are established, and that is how we quote it.
Processes usually combined with this work
Start your project.
Initial response within one business day.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer gives an initial response, typically within one business day. A written quotation typically follows within 7-10 business days after we receive the required information and complete any prerequisite NDA.